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 EMIF02-MIC03M6
2-line IPADTM, EMI filter and ESD protection for microphone
Features
Pin 1

EMI symmetrical (I/O) low-pass filter High efficiency in EMI filtering Very low PCB space consumption: 1.0 mm x 1.45 mm Very thin package: 0.6 mm max High efficiency in ESD suppression High reliability offered by monolithic integration High reduction of parasitic elements through integration and wafer level packaging. Lead-free and halogen-free package
Micro QFN 6 leads 1.45 mm x 1.00 mm (bottom view)
Figure 1.
Pin configuration (top view)
Complies with following standards
IEC 61000-4-2 level 4, input and output pins - 8 kV (contact discharge)
MICR in
1
6
MICR out
Application
GND MICL in
2
5
GND MICL out
Mobile phones
3
4
Description
The EMIF02-MIC03M6 is a 2-line highly integrated device designed to suppress EMI/RFI noise in all systems exposed to electromagnetic interference. This filter includes ESD protection circuitry, which prevents damage to the application when subjected to ESD surges up to 8 kV on all pins.
Figure 2.
Basic cell configuration
Low-pass filter
Input
Output
GND
GND
GND
R = 68 , Cline = 45 pF typ.
TM: IPAD is a trademark of STMicroelectronics
February 2008
Rev 1
1/10
www.st.com
Characteristics
EMIF02-MIC03M6
1
Table 1.
Symbol VPP Tj Top Tstg
Characteristics
Absolute ratings (limiting values at Tamb = 25 C unless otherwise specified)
Parameter ESD discharge IEC61000-4-2 contact discharge Junction temperature Operating temperature range Storage temperature range Value 8 125 -40 to + 85 -55 to +150 Unit kV C C C
Table 2.
Symbol VBR IRM VRM VCL Rd IPP RI/O Cline Symbol VBR IRM RI/O Cline
(1)
Electrical characteristics (Tamb = 25 C)
Parameter
I
Breakdown voltage Leakage current @ VRM Stand-off voltage Clamping voltage Dynamic resistance Peak pulse current Series resistance between Input & Output Input capacitance per line Test conditions IR = 1 mA VRM = 3 V per line Tolerance 20% VR = 0 V, F = 1 MHz, VOSC = 30 mV 68 45 Min. 6 Typ. 8
VCL VBR VRM
IPP
IR IRM IRM IR VRM VBR VCL
V
IPP
Max.
Unit V
500
nA pF
1. Tolerance 20%
Figure 3.
dB
S21 attenuation measurement
Figure 4.
dB
Analog cross talk measurements (MIC R / MIC L)
0.00 -5.00 -10.00 -15.00 -20.00 -25.00 -30.00 -35.00 -40.00
0.00 -10.00 -20.00 -30.00 -40.00 -50.00 -60.00
F (Hz)
300.0k 1.0M 3.0M 10.0M 30.0M 100.0M 300.0M 1.0G 3.0G
-70.00 -80.00 300.0k
F (Hz)
1.0M 3.0M Xtalk R- L 10.0M 30.0M 100.0M 300.0M 1.0G Xtalk L-R 3.0G
2/10
EMIF02-MIC03M6
Ordering information scheme
Figure 5.
ESD response to IEC 61000-4-2 (+8 kV air discharge) on MIC lines
Figure 6.
ESD response to IEC 61000-4-2 (-8 kV air discharge) on MIC lines
vi = 20 V/d
vi = 20 V/d
Input
Input
vo = 10 V/d
vo = 10 V/d
Output
Output
20 ns/d
20 ns/d
2
Ordering information scheme
Figure 7. Ordering information scheme
EMIF EMI Filter Number of lines Information xxx = application zz = version Package Mx = Micro QFN x leads
yy
-
xxx zz
Mx
3/10
Package information
EMIF02-MIC03M6
3
Package information
Epoxy meets UL94, V0
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at www.st.com. Table 3. Micro QFN 1.45 x 1.00 6L dimensions
D
N
Dimensions Ref.
E
Millimeters Min. Typ. 0.55 0.02 0.25 1.45 1.00 0.50 0.20 0.30 0.35 0.40 0.008 Max. 0.60 0.05 0.30 Min.
Inches Typ. Max.
1
2
A A1
0.50 0.00 0.18
0.020 0.022 0.024 0.000 0.001 0.002 0.007 0.010 0.012 0.057 0.039 0.020
A A1
1 2
b D
L k b e
E e K L
0.012 0.014 0.016
Figure 8.
Footprint in mm [inches]
0.50 [0.020] 0.25 [0.010]
Figure 9.
Marking
Dot : Pi n 1 Identification
0.60 [0.023] 0.30 1.60 [0.012] [0.063]
L
4/10
EMIF02-MIC03M6 Figure 10. Tape and reel specification
Dot identifying pin 1 location
2.0+/-0.05 4.00+/-0.1 1.5 +/- 0.1
Package information
1.75 +/- 0.1 3.5 +/- 0.03
0.75
All dimensions in mm
8.0 +/- 0.3
1.65
L
L
L
1.20 User direction of unreeling
4.00
Note:
Product marking may be rotated by 90 for assembly plant differentiation. In no case should this product marking be used to orient the component for its placement on a PCB. Only pin 1 mark is to be used for this purpose.
5/10
Recommendation on PCB assembly
EMIF02-MIC03M6
4
4.1
Recommendation on PCB assembly
Stencil opening design
1. General recommendation on stencil opening design a) Stencil opening dimensions: L (Length), W (Width), T (Thickness).
Figure 11. Stencil opening dimensions
L
T
W
b)
General design rule Stencil thickness (T) = 75 ~ 125 m W Aspect Ratio = ---- 1.5 T Lx W Aspect Area = --------------------------- 0.66 2T ( L + W )
2.
Reference design a) b) Stencil opening thickness: 100 m Stencil opening for leads: Opening to footprint ratio is 90%.
Figure 12. Recommended stencil window position
7 m
7 m 15 m
650 m
620 m 236 m 15 m 250 m
Footprint
Stencil window Footprint
6/10
EMIF02-MIC03M6
Recommendation on PCB assembly
4.2
Solder paste
1. 2. 3. 4. Halide-free flux qualification ROL0 according to ANSI/J-STD-004. "No clean" solder paste is recommended. Offers a high tack force to resist component movement during high speed. Solder paste with fine particles: powder particle size is 20-45 m.
4.3
Placement
1. 2. 3. 4. Manual positioning is not recommended. It is recommended to use the lead recognition capabilities of the placement system, not the outline centering. Standard tolerance of 0.05 mm is recommended. 3.5 N placement force is recommended. Too much placement force can lead to squeezed out solder paste and cause solder joints to short. Too low placement force can lead to insufficient contact between package and solder paste that could cause open solder joints or badly centered packages. To improve the package placement accuracy, a bottom side optical control should be performed with a high resolution tool. For assembly, a perfect supporting of the PCB (all the more on flexible PCB) is recommended during solder paste printing, pick and place and reflow soldering by using optimized tools.
5. 6.
4.4
PCB design preference
1. 2. To control the solder paste amount, the closed via is recommended instead of open vias. The position of tracks and open vias in the solder area should be well balanced. The symmetrical layout is recommended, in case any tilt phenomena caused by asymmetrical solder paste amount due to the solder flow away.
7/10
Recommendation on PCB assembly
EMIF02-MIC03M6
4.5
Reflow profile
Figure 13. ST ECOPACK(R) recommended soldering reflow profile for PCB mounting
Temperature (C)
260C max 255C 220C 180C 125 C
2C/s recommended 2C/s recommended 6C/s max 6C/s max
3C/s max 3C/s max
0 0 1 2 3 4 5
10-30 sec 90 to 150 sec 90 sec max
6
7
Time (min)
Note:
Minimize air convection currents in the reflow oven to avoid component movement.
8/10
EMIF02-MIC03M6
Ordering information
5
Ordering information
Table 4. Ordering information
Marking L(1) Package Micro QFN Weight 2.2 mg Base qty 3000 Delivery mode Tape and reel (7")
Order code EMIF02-MIC03M6
1. The marking can be rotated by 90 to differentiate assembly location
6
Revision history
Table 5.
Date 13-Feb-2008
Document revision history
Revision 1 Initial release Changes
9/10
EMIF02-MIC03M6
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10/10


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